1. Field of the Invention
The present disclosure relates generally to accessing data, and more particularly, to obtaining data, and a storage key when appropriate, alter storage address translation in a system with pipelined processors.
2. Description of Background
Multiprocessor systems comprise a plurality of processors, each of which may at some point need access to main memory. This need for memory accesses may arise simultaneously with respect to two or more of the processors in the multi processing system. Such systems may comprise intermediate level caches for temporarily storing instructions and data. A cache memory, or cache, is a high-speed memory positioned between a processor and main storage to hold recently accessed main storage data. When data in storage is requested in a processor system, a determination is first made whether or not the data is in the cache. If the data is in the cache, it is accessed from the cache. If the data is not in the cache, then the data is obtained from the main storage. The data obtained from the main storage is then stored in the cache, usually replacing other data that had been previously stored in the cache.
A cache hierarchy may exist, in which multiple levels of caches exist between the processor and main storage. For example, a multiprocessing system may include a first level or primary cache storage (L1) that is closest to the processor and one or more intermediate levels of memory or caches that are closer to the main memory, e.g., intermediate caches (L2, L3, . . . LN). The L1 cache may be considered the bottom-most cache, and LN cache may be considered the highest-level cache. As the cache levels get farther away from the processor, each cache gets larger, slower, and cheaper.
In a virtual memory system, a memory access request usually includes a virtual address (VA) (also referred to as a logical address or effective address) known to the associated program. The real address (RA) (also referred to as an absolute address or physical address) in main memory associated with a VA can be determined through a translation process. The translation process is a multi-cycle, multi-step process that involves table lookups to get the RA.
To speed up the translation, a translation look-aside buffer (TLB) (also known as dlat or erat) is used. A TLB holds the VA and corresponding RA for recent translations. The TLB is similar to a data cache. It is a cache for storing translations.
A cache has a corresponding directory array, which holds the addresses of the data currently in the cache. Each address corresponds to a unit of storage called a line. The address that is stored within a directory array entry is called a tag.
When a request for data is sent from the core (processor core) to the L1 cache, the request address is compared against the addresses in the directory to see if the corresponding requested data is in the L1 cache. The range of address bits that is used to address the directory is called a directory index or congruence class. In order to access the data from a L1 cache with a directory that is absolute address managed based on the virtual address obtained through a program instruction, the corresponding absolute address is needed.
Although the L1 cache can be designed as virtual address based, higher level caches in the hierarchy, e.g., L2, L3, etc., and most importantly, main memory are absolute address based. Therefore, if a cache miss occurs, the absolute address is required to obtain desired data.
There are many possible virtual to real address translations, and all the translations cannot be held in the TLB. If the RA corresponding to the VA included in a data request is not stored in the TLB, a TLB “miss” occurs. If a TLB miss occurs, the translation from VA to RA may be obtained from a Translator Unit (XU).
After getting a Dynamic Address Translation (DAT) result from the XU in the event of a TLB miss, the obtained absolute address can be used to fetch the cache line from the L2 cache if the line is not in the primary (L1) cache. Often times, the address that missed in the TLB also misses the L1 cache. It is not desirable to wait through the pipeline delays needed to perform a primary cache directory lookup using the absolute address received after a TLB miss before sending a request to the L2 cache to obtain the desired data, since most likely the line is not available in the L1 cache.
Depending on architectural requirements, the TLB may need more fields than just the VA and corresponding RA to provide the requested translation. A storage key is one of these fields. As those skilled in the art would appreciate, the storage key is used by software or operating systems for storage access protection. It is usually defined for a particular page of memory, such that user programs need to have the correct access keys in order to read or write to a particular storage within a page.
However, after a TLB miss, and the XU does not provide the storage key for the absolute address, the key needs to be fetched from the upper level caches or memory in order to write a complete entry (absolute address and storage key) into the TLB. The requirement to always obtain a key on a TLB miss also drives the desire to have a mechanism that can make a key fetch request to L2 cache as early as possible.